This invention relates to a bit circuit for use in programmable logic arrays formed on integrated-circuit chips and, in particular, to what is commonly known as a "zero-power" bit circuit formed using complementary-metal-oxide-semiconductor (CMOS) processes.
Known previous attempts at constructing zero-power bit circuits in integrated form have utilized either cross-coupled inverters with stable states skewed by coupling capacitors to the power supplies or have utilized CMOS technology related to electrically-erasable-read-only-memory (EEPROM) devices. Bit circuits using cross-coupled inverters depend upon well-controlled power-up sequences for proper initialization of the circuit at the time the power source is connected and, if the bit setting is disturbed by unwanted transients occurring during operation, resetting of the bit will not occur until the next such power-up sequence is applied to the circuit. Bit circuits formed using EEPROM technology are generally limited to use in circuit designs that have EEPROM capability.
In my pending U.S. Pat. Application Ser. No. 07/183,957, I have described a zero-power bit circuit that is compatible with existing CMOS technology and that requires no special power-up sequence of signals. One element of the bit circuit embodiments described in that patent application is a transistor pair with common floating gates as described in abandoned U.S. Pat. Application No. 065,989 by Howard L. Tigelaar, entitled "Floating Gate Semiconductor Device", filed June 24, 1987 and assigned to Texas Instruments Incorporated. The floating gate to the transistor pair used in the bit circuit of my pending U.S. Pat. Application Ser. No. 07/183,957 requires additional steps of levels of processing during manufacture, as compared to steps of levels of processing using transistors without such floating gates located between gates and channels.
Accordingly, there is a need for a zero-power bit circuit that requires no special power-up sequence of signals and that can be constructed using a single polysilicon gate level process. A bit circuit comprised solely of transistors with single-level polysilicon gates is particularly needed for construction of logic arrays that require relatively few programmable cells and that are otherwise comprised of circuitry that does not require the extra level of processing for fabrication of standard floating-gate transistors.
In my pending U.S. Pat. Application Ser. No. 07/183,956, I have described a zero-power bit circuit that can be constructed solely of transistors with single-level polysilicon gates. The bit circuit of this invention is an alternative to the bit circuit described in that application.